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Figure 7.3 Three different DRAM memory cell structures: (a) planar capacitor DRAM cell; (b) stack capacitor DRAM cell; (c) trench capacitor DRAM cell. charged to a "low" voltage, which is usually the ground, the memory cell stores a "0" state. Figure 7.3 illustrates the physical implementation of the three types of DRAM cell structure. Figure 7.3a shows a "planar" cell where the capacitor dielectric film is formed between the planar n+-doped silicon surface and the upper heavily doped polysilicon layer. This structure was used in early generations of DRAMs with a density of up to 1 Mb, but is no longer used because the capacitor occupies too much area to permit high density. Figure 7.3b shows a "stack"-type structure where the capacitor dielectric is formed between the two heavily doped polysilicon layers and is stacked over the MOS pass transistor. Figure 7.3c shows a "trench"-type structure where the capacitor dielectric is formed inside a trench etched into the silicon substrate and between the n+-doped silicon and the upper, heavily doped polysilicon layer. The details of these structures are further described in the next section. 7.2.2 Cell Scaling

ELECTRONIC MAIL (E-MAIL)

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Note that the phase of the transmit signal can jump at the bit transitions. This leads to undesirable spectral properties. The power spectrum of FSK can be shown to consist of a continuous and a discrete (spectral lines) part: S(f ) = Scont (f ) + Sdisc (f ) where (see Benedetto and Biglieri [1999]): 2 1 1 |Gm (f )|2 Scont (f ) = 2T 2

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We illustrate the application of the various formalisms to 0.1-jtm-channel-length MOSFETs, using TMA MEDICI 17 simulations. In Figure 4.5 we show a sequence of 2D plots of the carrier concentration profiles, equipotential contours, and the equienergy contours in the channel region of the NMOSFET using three types of models: low-field mobility in the drift-diffusion equation, field-dependent mobility in the drift-diffusion equation, and finally the energy-balance equation. We also show the ID cuts along the channel, showing the longitudinal electric field profile, along with a cut of the electron energy contours. Comparing the field-dependent model, with the full energy-balance model, one sees that there is less carrier heating near the drain end in the latter case. This is because there is a divergence of the energy flux from the high-temperatura region, leading to some cooling of the carriers. One also finds that in the energy-balance case, the carrier energies do not track the local electric field, because the past history of the carrier motion has to be taken into account. Such high-field effects are clearly very important for miniaturized ULSI MOS devices to model substrate current (which involves impact ionization across the 1.1-eV Si bandgap), gate current (which involves electron injection across the 3.1-eV conduction band-edge discontinuity between Si and Si0 2), and velocity overshoot effects, which can increase the drain current in deepsubmicrometer MOSFETs. The output currents are higher in the energy-balance case because if there is less carrier heating, there is less high-field channel mobility degradation.

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